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L6728
Single phase PWM controller with Power Good
Features

Flexible power supply from 5 V to 12 V Power conversion input as low as 1.5 V 0.8 V internal reference 0.8 % output voltage accuracy High-current integrated drivers Power Good output Sensorless and programmable OCP across low-side RDS(on) OV / UV protections VSEN disconnection protection Oscillator internally fixed at 300 kHz LSless to manage pre-bias start-up Adjustable output voltage Disable function Internal soft-start DFN10 package DFN10
Description
L6728 is a single-phase step-down controller with integrated high-current drivers that provides complete control logic and protection to realize in a simple way general DC-DC converters by using a compact DFN10 package. Device flexibility allows managing conversions with power input VIN as low as 1.5 V and device supply voltage ranging from 5 V to 12 V. L6728 provides simple control loop with voltage mode EA. The integrated 0.8 V reference allows regulating output voltages with 0.8 % accuracy over line and temperature variations. Oscillator is internally fixed to 300 kHz. L6728 provides programmable dual level over current protection as well as over and under voltage protection. Current information is monitored across the low-side MOSFET RDS(on) saving the use of expensive and spaceconsuming sense resistors. PGOOD output easily provides real-time information on output voltage status, through VSEN dedicated output monitor.
Applications

Memory and termination supply Subsystem power supply (MCH, IOCH, PCI...) CPU and DSP power supply Distributed power supply General DC-DC converters
Table 1.
Device summary
Order codes L6728 DFN10 L6728TR Tape and reel Package Packaging Tube
June 2008
Rev 3
1/31
www.st.com 1
Content
L6728
Content
1 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 4
1.1 1.2 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 4
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 4.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 6
Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.1 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.1 Low-side-less start up (LSLess) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
8
Over current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8.1 Over current threshold setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
9 10
Output voltage setting and protections . . . . . . . . . . . . . . . . . . . . . . . . 14 Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
10.1 10.2 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
11
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
11.1 11.2 11.3 Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Output capacitor(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/31
L6728
Content
12
20 A demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
12.1 Board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
12.1.1 12.1.2 12.1.3 12.1.4 12.1.5 Power input (Vin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Output (Vout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Signal input (Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Test points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Board characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
13
5 A demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
13.1 Board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
13.1.1 13.1.2 13.1.3 13.1.4 13.1.5 Power input (Vin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Output (Vout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Signal input (Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Test points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Board characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
14 15
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3/31
Typical application circuit and block diagram
L6728
1
1.1
Typical application circuit and block diagram
Application circuit
Figure 1. Typical application circuit
VIN = 1.5V to 12V VCC = 5V to 12V CDEC RPG PGOOD 10 PGOOD 6 VCC BOOT 1 CHF HS L Vout CBULK
COMP / DIS
L6728
7
UGATE
3
CF CP RF 8
PHASE
2
FB VSEN 9
LGATE / OC GND 5
4
LS
COUT
LOAD
ROS
RFB
ROCSET
ROS
L6728 Reference Schematic
RFB
1.2
Block diagram
Figure 2. Block diagram
VCC
VOUT MONITOR CONTROL LOGIC & PROTECTIONS
VSEN
OC
VOCTH
PGOOD
BOOT
ADAPTIVE ANTI CROSS CONDUCTION
CLOCK
HS
UGATE PHASE
PWM 300 kHz OSCILLATOR ERROR AMPLIFIER + -
VCC
LS
LGATE / OC GND
L6728
COMP / DIS FB
0.8V IOCSET
4/31
L6728
Pin description and connection diagrams
2
Pin description and connection diagrams
Figure 3. Pin connection (top view)
2.1
Pin descriptions
Table 2.
Pin #
Pins description
Name Function HS driver supply. Connect through a capacitor (100 nF) to the floating node (LS-Drain) pin and provide necessary bootstrap diode from VCC. HS driver return path, current-reading and adaptive-dead-time monitor. Connect to the LS drain to sense RDS(on) drop to measure the output current. This pin is also used by the adaptive-dead-time control circuitry to monitor when HS MOSFET is OFF. HS driver output. Connect directly to HS MOSFET gate.
1
BOOT
2
PHASE
3
UGATE
4
LGATE. LS driver output. Connect directly to LS MOSFET gate. OC. Over Current threshold set. During a short period of time following VCC rising over UVLO threshold, a 10 A current is sourced from this pin. resistor greater than 5 k to program OC LGATE / OC Connect to GND with an ROCSET Threshold. The resulting voltage at this pin is sampled and held internally as the OC set point. Maximum programmable OC threshold is 0.55 V. A voltage greater than 0.6 V activates an internal clamp and causes OC threshold to be set at the maximum value. GND VCC All internal references, logic and drivers are connected to this pin. Connect to the PCB ground plane. Device and drivers power supply. Operative range from 5 V to 12 V. Filter with at least 1 nF MLCC to GND.
5 6
7
COMP. Error amplifier output. Connect with an RF - CF // CP to FB to compensate the device control loop. COMP / DIS DIS. The device can be disabled by pushing this pin lower than 0.75 V(typ). Setting free the pin, the device enables again. FB Error amplifier inverting input. Connect with a resistor RFB to the output regulated voltage. Output resistor divider may be used to regulate voltages higher than the reference.
8
5/31
Thermal data Table 2.
Pin # 9
L6728 Pins description (continued)
Name VSEN Function Regulated voltage sense pin for OVP and UVP protections and PGOOD. Connect to the output regulated voltage, or to the output resistor divider if the regulated voltage is higher than the reference. Open drain output set free after SS has finished and pulled low when VSEN is outside the relative window. Pull up to a voltage equal or lower than VCC. If not used it can be left floating.
10
PGOOD
3
Thermal data
Table 3.
Symbol Rth(JA) Rth(JC) TMAX TSTG TJ PTOT
Thermal data
Parameter Thermal resistance junction to ambient (Device soldered on 2s2p, 67 mm x 69 mm board) Thermal resistance junction to case Maximum junction temperature Storage temperature range Junction temperature range Maximum power dissipation at TA = 25 C Value 45 5 150 -40 to 150 -40 to 125 2.25 Unit C/W C/W C C C W
6/31
L6728
Electrical specifications
4
4.1
Electrical specifications
Absolute maximum ratings
Table 4.
Symbol VCC VBOOT, VUGATE to GND to PHASE to GND to GND; t < 200 ns to GND to GND; t < 200 ns to GND FB, COMP, VSEN to GND PGOOD to GND
Absolute maximum ratings
Parameter Value -0.3 to 15 15 33 45 -5 to 18 -8 to 30 -0.3 to VCC+0.3 -0.3 to 3.6 -0.3 to VCC+0.3 Unit V V
VPHASE VLGATE
V V V V
4.2
Table 5.
Symbol
Electrical characteristics
Electrical characteristics (VCC = 5 V to 12 V; TJ = 0 to 70 C unless otherwise specified)
Parameter Test conditions Min Typ Max Unit
Supply current and power-ON ICC IBOOT UVLO Hysteresis Oscillator FSW VOSC dMAX Main oscillator accuracy PWM ramp amplitude Maximum duty cycle 80 270 300 1.4 330 kHz V % 0.2 V VCC supply current BOOT supply current VCC Turn-ON UGATE and LGATE = OPEN UGATE = OPEN; PHASE to GND VCC rising 6 0.7 4.1 mA mA V
Reference and error amplifier Output voltage accuracy A0 GBWP SR DIS DC gain
(1) (1)
-0.8
120 15 8
0.8
% dB MHz V/s
Gain-bandwidth product Slew-rate
(1)
Disable threshold
COMP falling
0.70
0.85
V
7/31
Electrical specifications Table 5.
Symbol Gate drivers IUGATE RUGATE ILGATE RLGATE HS source current HS sink resistance LS source current LS sink resistance BOOT - PHASE = 5 V BOOT - PHASE = 5 V VCC = 5 V VCC = 5 V 1.5 1.1 1.5 0.65
L6728
Electrical characteristics (continued) (VCC = 5 V to 12 V; TJ = 0 to 70 C unless otherwise specified)
Parameter Test conditions Min Typ Max Unit
A A
Over-current protection IOCSET VOC_SW OCSET current source OC switch-over threshold Sourced from LGATE pin, during OC setting phase. VLGATE/OC rising 9 10 600 11 A mV
Over and under-voltage protections VSEN rising OVP UVP VSEN PGOOD Upper threshold PGOOD Lower threshold VPGOODL PGOOD voltage low VSEN falling IPGOOD = -4 mA 0.680 0.710 0.740 0.4 V V VSEN rising 0.860 0.890 0.920 V OVP threshold un-latch, VSEN falling UVP threshold VSEN bias current VSEN falling Sourced from VSEN 0.35 0.50 0.40 0.60 100 0.45 0.70 V V nA 0.90 1.00 1.10 V
1. Guaranteed by design, not subject to test.
8/31
L6728
Device description
5
Device description
L6728 is a single-phase PWM controller with embedded high-current drivers that provides complete control logic and protections to realize in an easy and simple way a general DCDC step-down converter. Designed to drive N-channel MOSFETs in a synchronous buck topology, with its high level of integration this 10-pin device allows reducing cost and size of the power supply solution also providing real-time PGOOD in a compact DFN10 3x3 mm. L6728 is designed to operate from a 5 V or 12 V supply. The output voltage can be precisely regulated to as low as 0.8 V with 0.8 % accuracy over line and temperature variations. The switching frequency is internally set to 300 kHz. This device provides a simple control loop with a voltage-mode error-amplifier. The erroramplifier features a 15 MHz gain-bandwidth product and 8V/s slew rate, allowing high regulator bandwidth for fast transient response. To avoid load damages, L6728 provides over current protection as well as over voltage, under voltage and feedback disconnection protection. The over current trip threshold is programmable by a simple resistor connected from Lgate to GND. Output current is monitored across low-side MOSFET RDS(on), saving the use of expensive and spaceconsuming sense resistor. Output voltage is monitored through dedicated VSEN pin. L6728 implements soft-start increasing the internal reference in closed loop regulation. Low-side-less feature allows the device to perform soft-start over pre-biased output avoiding high current return through the output inductor and dangerous negative spike at the load side. L6728 is available in a compact DFN10 3x3 mm package with exposed pad.
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Driver section
L6728
6
Driver section
The integrated high-current drivers allow using different types of power MOSFET (also multiple MOSFETs to reduce the equivalent RDS(on)), maintaining fast switching transition. The driver for the high-side MOSFET uses BOOT pin for supply and PHASE pin for return. The driver for low-side MOSFET uses the VCC pin for supply and GND pin for return. The controller embodies an anti-shoot-through and adaptive dead-time control to minimize low side body diode conduction time, maintaining good efficiency while saving the use of Schottky diode:

to check high-side MOSFET turn off, PHASE pin is sensed. When the voltage at PHASE pin drops down, the low-side MOSFET gate drive is suddenly applied; to check low-side MOSFET turn off, LGATE pin is sensed. When the voltage at LGATE has fallen, the high-side MOSFET gate drive is suddenly applied.
If the current flowing in the inductor is negative, voltage on PHASE pin will never drop. To allow the low-side MOSFET to turn-on even in this case, a watchdog controller is enabled: if the source of the high-side MOSFET doesn't drop, the low side MOSFET is switched on so allowing the negative current of the inductor to recirculate. This mechanism allows the system to regulate even if the current is negative. Power conversion input is flexible: 5 V, 12 V bus or any bus that allows the conversion (See maximum duty cycle limitations) can be chosen freely.
6.1
Power dissipation
L6728 embeds high current MOSFET drivers for both high side and low side MOSFETs: it is then important to consider the power that the device is going to dissipate in driving them in order to avoid overcoming the maximum junction operative temperature. Two main terms contribute in the device power dissipation: bias power and drivers' power.
Device bias power (PDC) depends on the static consumption of the device through the supply pins and it is simply quantifiable as follow (assuming to supply HS and LS drivers with the same VCC of the device):
P DC = V CC ( I CC + I BOOT )
Drivers power is the power needed by the driver to continuously switch on and off the external MOSFETs; it is a function of the switching frequency and total gate charge of the selected MOSFETs. It can be quantified considering that the total power PSW dissipated to switch the MOSFETs (easy calculable) is dissipated by three main factors: external gate resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance. This last term is the important one to be determined to calculate the device power dissipation. The total power dissipated to switch the MOSFETs results:
P SW = F SW ( Q gHS V BOOT + Q gLS V CC )
External gate resistors helps the device to dissipate the switching power since the same power PSW will be shared between the internal driver impedance and the external resistor resulting in a general cooling of the device.
10/31
L6728
Soft-start
7
Soft-start
L6728 implements a soft-start to smoothly charge the output filter avoiding high in-rush currents to be required from the input power supply. The device gradually increases the internal reference from 0 V to 0.8 V in 4.5 ms (typ.), in closed loop regulation, linearly charging the output capacitors to the final regulation voltage. In the event of an over current triggering during soft start, the over current logic will override the soft start sequence and will shut down the PWM logic and both the high side and low side gates. This condition is latched, cycle VCC to recover. The device begins soft start phase only when VCC power supply is above UVLO threshold and over current threshold setting phase has been completed.
7.1
Low-side-less start up (LSLess)
In order to avoid any kind of negative undershoot and dangerous return from the load during start-up, L6728 performs a special sequence in enabling LS driver to switch: during the softstart phase, the LS driver results disabled (LS = OFF) until the HS starts to switch. This avoid the dangerous negative spike on the output voltage that can happen if starting over a pre-biased output. If the output voltage is pre-biased to a voltage higher than the final one, the HS would never start to switch. In this case, at the end of soft start time, LS is enabled and discharge the output to the final regulation value. This particular feature of the device masks the LS turn-on only from the control loop point of view: protections by-pass this turning ON the LS MOSFET in case of need. Figure 4. LSLess start up (left) vs non-LSLess start up (right)
11/31
Over current protection
L6728
8
Over current protection
The over current function protects the converter from a shorted output or overload, by sensing the output current information across the low side MOSFET drain-source onresistance, RDS(on). This method reduces cost and enhances converter efficiency by avoiding the use of expensive and space-consuming sense resistors. The low side RDS(on) current sense is implemented by comparing the voltage at the PHASE node when LS MOSFET is turned on with the programmed OCP thresholds voltages, internally held. If the monitored voltage is bigger than these thresholds, an over current event is detected. For maximum safety and load protection, L6728 implements a dual level over current protection system:
1st level threshold: it is the user externally set threshold. If the monitored voltage on PHASE exceeds this threshold, a 1st level over current is detected. If four 1st level OC events are detected in four consecutive switching cycles, over current protection will be triggered. 2nd level threshold: it is an internal threshold whose value is equal to 1st level threshold multiplied by a factor 1.5. If the monitored voltage on PHASE exceeds this threshold, over current protection will be triggered immediately.
When over current protection is triggered, the device turns off both LS and HS MOSFETs in a latched condition. To recover from over current protection triggered condition, VCC power supply must be cycled.
12/31
L6728
Over current protection
8.1
Over current threshold setting
L6728 allows to easily program a 1st level over current threshold ranging from 50 mV to 550 mV, simply by adding a resistor (ROCSET) between LGATE and GND. 2nd level threshold will be automatically set accordingly. During a short period of time (about 5 ms) following VCC rising over UVLO threshold, an internal 10 A current (IOCSET) is sourced from LGATE pin, determining a voltage drop across ROCSET. This voltage drop will be sampled and internally held by the device as 1st level over current threshold. The OC setting procedure overall time length is about 5 ms. Connecting a ROCSET resistor between LGATE and GND, the programmed 1st level threshold will be:
I OCSET R OCSET I OCth1 = ------------------------------------------R dsON
the programmed 2nd level threshold will be:
I OCSET R OCSET I OCth2 = 1.5 ------------------------------------------R dsON
ROCSET values range from 5 k to 55 k. In case ROCSET is not connected, the device sets the OCP thresholds to the maximum values: an internal safety clamp on LGATE is triggered as soon as LGATE voltage reaches 600 mV, setting the maximum threshold and suddenly ending OC setting phase.
13/31
Output voltage setting and protections
L6728
9
Output voltage setting and protections
L6728 is capable to precisely regulate an output voltage as low as 0.8 V. In fact, the device comes with a fixed 0.8 V internal reference that guarantee the output regulated voltage to be within 0.8 % tolerance over line and temperature variations (excluding output resistor divider tolerance, when present). Output voltage higher than 0.8 V can be easily achieved by adding a resistor ROS between FB pin and ground. Referring to Figure 1, the steady state DC output voltage will be:
R FB V OUT = V REF 1 + ---------- R
OS
where VREF is 0.8 V. L6728 monitors the voltage at VSEN pin and compares it to internal reference voltage in order to provide under voltage and over voltage protections as well as PGOOD signal. According to the level of VSEN, different actions are performed from the controller:
PGOOD If the voltage monitored through VSEN exits from the PGOOD window limits, the device de-asserts the PGOOD signal still continuing switching and regulating. PGOOD is asserted at the end of the soft-start phase.
Under voltage protection If the voltage at VSEN pin drops below UV threshold, the device turns off both HS and LS MOSFETs, latching the condition. Cycle VCC to recover.
Over voltage protection If the voltage at VSEN pin rises over OV threshold (1 V typ), over voltage protection turns off HS MOSFET and turns on LS MOSFET. The LS MOSFET will be turned off as soon as VSEN goes below Vref/2 (0.4 V). The condition is latched, cycle VCC to recover. Notice that, even if the device is latched, the device still controls the LS MOSFET and can switch it on whenever VSEN rises above OV threshold.
Feedback disconnection protection In order to provide load protection even if VSEN pin is not connected, a 100 nA bias current is always sourced from this pin. If VSEN pin is not connected, this current will permanently pull it up causing the device to detect an OV: thus LS will be latched on preventing output voltage from rising out of control.
14/31
L6728
Application details
10
10.1
Application details
Compensation network
The control loop showed in Figure 5 is a voltage mode control loop. The output voltage is regulated to the internal reference (when present, offset resistor between FB node and GND can be neglected in control loop calculation). Error Amplifier output is compared to oscillator saw-tooth waveform to provide PWM signal to the driver section. PWM signal is then transferred to the switching node with VIN amplitude. This waveform is filtered by the output filter. The converter transfer function is the small signal transfer function between the output of the EA and VOUT. This function has a double pole at frequency FLC depending on the L-COUT resonance and a zero at FESR depending on the output capacitor ESR. The DC Gain of the modulator is simply the input voltage VIN divided by the peak-to-peak oscillator voltage VOSC. Figure 5. PWM control loop
VIN OSC V OSC
_ + PWM COMPARATOR ERROR AMPLIFIER + _
L
R COUT ESR
V OUT
VREF RFB
CF CP
RF
CS ZF
RS ZFB
The compensation network closes the loop joining VOUT and EA output with transfer function ideally equal to -ZF/ZFB. Compensation goal is to close the control loop assuring high DC regulation accuracy, good dynamic performances and stability. To achieve this, the overall loop needs high DC gain, high bandwidth and good phase margin. High DC gain is achieved giving an integrator shape to compensation network transfer function. Loop bandwidth (F0dB) can be fixed choosing the right RF/RFB ratio, however, for stability, it should not exceed FSW/2. To achieve a good phase margin, the control loop gain has to cross 0 dB axis with -20 dB/decade slope. As an example, Figure 6 shows an asymptotic bode plot of a type III compensation.
15/31
Application details Figure 6. Example of type III compensation
Gain [dB] open loop EA gain FZ1 FZ2 closed loop gain compensation gain open loop converter gain 0dB F0dB FLC FESR 20log (RF/RFB) 20log (VIN/VOSC ) Log (Freq) FP1 FP2
L6728
Open loop converter singularities: a) b)
1 F LC = --------------------------------2 L C OUT 1 F ESR = ------------------------------------------2 C OUT ESR
Compensation network singularities frequencies: a) b) c)
1 F Z1 = -----------------------------2 R F C F 1 F Z2 = ---------------------------------------------------2 ( R FB + R S ) C S 1 F P1 = ------------------------------------------------CF CP 2 R F -------------------- C F + C P 1 F P2 = -----------------------------2 R S C S
d)
To place the poles and zeroes of the compensation network, the following suggestions may be followed: a) Set the gain RF/RFB in order to obtain the desired closed loop regulator bandwidth according to the approximated formula (suggested values for RFB are in the range of some k):
F 0dB V OSC RF ---------- = ------------ -----------------F LC V IN R FB
16/31
L6728
Application details
b)
Place FZ1 below FLC (typically 0.5*FLC):
1 C F = ---------------------------- R F F LC
c)
Place FP1 at FESR:
CF C P = ---------------------------------------------------------2 R F C F F ESR - 1
d)
Place FZ2 at FLC and FP2 at half of the switching frequency:
R FB R S = -------------------------F SW ----------------- - 1 2 F LC 1 C S = ----------------------------- R S F SW
e) f)
Check that compensation network gain is lower than open loop EA gain before F0dB; Check phase margin obtained (it should be greater than 45) and repeat if necessary.
10.2
Layout guidelines
L6728 provides control functions and high current integrated drivers to implement highcurrent step-down DC-DC converters. In this kind of application, a good layout is very important. The first priority when placing components for these applications has to be reserved to the power section, minimizing the length of each connection and loop as much as possible. To minimize noise and voltage spikes (EMI and losses) power connections (highlighted in Figure 7) must be a part of a power plane and anyway realized by wide and thick copper traces: loop must be anyway minimized. The critical components, i.e. the power MOSFETs, must be close one to the other. The use of multi-layer printed circuit board is recommended. The input capacitance (CIN), or at least a portion of the total capacitance needed, has to be placed close to the power section in order to eliminate the stray inductance generated by the copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be connected near the HS drain. Use proper VIAs number when power traces have to move between different planes on the PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the same high-current trace on more than one PCB layer will reduce the parasitic resistance associated to that connection. Connect output bulk capacitors (COUT) as near as possible to the load, minimizing parasitic inductance and resistance associated to the copper trace, also adding extra decoupling capacitors along the way to the load when this results in being far from the bulk capacitors bank.
17/31
Application details Figure 7. Power connections (heavy lines)
VIN
L6728
UGATE PHASE
CIN L
L6728
LGATE GND COUT LOAD
Gate traces and phase trace must be sized according to the driver RMS current delivered to the power MOSFET. The device robustness allows managing applications with the power section far from the controller without losing performances. Anyway, when possible, it is recommended to minimize the distance between controller and power section. Small signal components and connections to critical nodes of the application, as well as bypass capacitors for the device supply, are also important. Locate bypass capacitor (VCC and Bootstrap capacitor) and feedback compensation components as close to the device as practical. For over current programmability, place ROCSET close to the device and avoid leakage current paths on LGATE / OC pin, since the internal current source is only 10 A. Systems that do not use Schottky diode in parallel to the low-side MOSFET might show big negative spikes on the phase pin. This spike must be limited within the absolute maximum ratings (for example, adding a gate resistor in series to HS MOSFET gate), as well as the positive spike, but has an additional consequence: it causes the bootstrap capacitor to be over-charged. This extra-charge can cause, in the worst case condition of maximum input voltage and during particular transients, that boot-to-phase voltage overcomes the absolute maximum ratings also causing device failures. It is then suggested in this cases to limit this extra-charge by adding a small resistor in series to the bootstrap diode. Figure 8.
LS DRIVER VCC CGD RGATE LGATE CGS CDS RINT UGATE CGS CDS RGATE RINT
Drivers turn-on and turn-off paths
LS MOSFET HS DRIVER BOOT CGD HS MOSFET
GND
PHASE
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L6728
Application information
11
11.1
Application information
Inductor design
The inductance value is defined by a compromise between the dynamic response time, the efficiency, the cost and the size. The inductor has to be calculated to maintain the ripple current (IL) between 20 % and 30 % of the maximum output current (typ). The inductance value can be calculated with the following relationship:
V IN - V OUT V OUT L = ----------------------------- -------------F SW I L V IN
Where FSW is the switching frequency, VIN is the input voltage and VOUT is the output voltage. Figure 9 shows the ripple current vs. the output voltage for different values of the inductor, with VIN = 5 V and VIN = 12 V. Increasing the value of the inductance reduces the current ripple but, at the same time, increases the converter response time to a dynamic load change. The response time is the time required by the inductor to change its current from initial to final value. Until the inductor has not finished its charging time, the output current is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance required. If the compensation network is well designed, during a load variation the device is able to set a duty cycle value very different (0 % or 80 %) from steady state one. When this condition is reached, the response time is limited by the time required to change the inductor current. Figure 9. Inductor current ripple vs output voltage
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Application information
L6728
11.2
Output capacitor(s)
The output capacitors are basic components to define the ripple voltage across the output and for the fast transient response of the power supply. They depend on the output voltage ripple requirements, as well as any output voltage deviation requirement during a load transient. During steady-state conditions, the output voltage ripple is influenced by both the ESR and capacitive value of the output capacitors as follow:
V OUT_ESR = I L ESR 1 V OUT_C = I L -------------------------------------8 C OUT F SW
Where IL is the inductor current ripple. In particular, the expression that defines VOUT_C takes in consideration the output capacitor charge and discharge as a consequence of the inductor current ripple. During a load variation, the output capacitors supplies the current to the load or absorb the current stored into the inductor until the converter reacts. In fact, even if the controller recognizes immediately the load transient and sets the duty cycle at 80 % or 0 %, the current slope is limited by the inductor value. The output voltage has a drop that also in this case depends on the ESR and capactive charge/discharge as follow:
V OUT_ESR = I OUT ESR L I OUT V OUT_C = I OUT ------------------------------------2 C OUT V L
Where VL is the voltage applied to the inductor during the transient response ( D MAX V IN - V OUT for the load appliance or VOUT for the load removal). MLCC capacitors have typically low ESR to minimize the ripple but also have low capacitance that do not minimize the voltage deviation during dynamic load variations. On the contrary, electrolytic capacitors have big capacitance to minimize voltage deviation during load transients while they does not show the same ESR values of the MLCC resulting then in higher ripple voltages. For these reasons, a mix between electrolytic and MLCC capacitor is suggeted to minimize ripple as well as reducing voltage deviation in dynamic mode.
11.3
Input capacitors
The input capacitor bank is designed considering mainly the input rms current that depends on the output deliverable current (IOUT) and the duty-cycle (D) for the regulation as follow:
I rms = I OUT D ( 1 - D )
The equation reaches its maximum value, IOUT/2, with D = 0.5. The losses depends on the input capacitor ESR and, in worst case, are:
P = ESR ( I OUT 2 )
2
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L6728
20 A demonstration board
12
20 A demonstration board
L6728 demonstration board realizes in a four-layer PCB a step-down DC/DC converter and shows the operation of the device in a general purpose application. The input voltage can range from 5 V to 12 V buses and the output voltage is fixed at 1.25 V. The application can deliver an output current up to 30 A. The switching frequency is 300 kHz. Figure 10. 20 A demonstration board (left) and components placement (right)
Figure 11. L6728 - 20 A demonstration board top (left) and bottom (right) layers
Figure 12. L6728 - 20 A demonstration board inner layers
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20 A demonstration board Figure 13. 20 A demonstration board schematic
L6728
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L6728 Table 6.
Qty Capacitors 2 1 3 2 2 2 1 1 1 C1, C2 C10 C11 to C13 C14, C38 C15, C19 C18, C20 C23 C24 C35
20 A demonstration board 20 A demonstration board - bill of material
Reference Description Package
Electrolytic capacitor 1800 F 16 V Nippon chemi-con KZJ or KZG MLCC, 100 nF, 16V, X7R MLCC, 4.7 F, 16V, X5R Murata GRM31CR61C475MA01 MLCC, 1 F, 16V, X7R MLCC, 10 F, 6.3 V, X7R Murata GRM31CR70J106KA01L Electrolytic capacitor 2200 F 6.3 V Nippon chemi-con KZJ or KZG MLCC, 6.8 nF, X7R MLCC, 33 nF, X7R MLCC, 68 pF, X7R
Radial 10 x 25 mm SMD0603 SMD1206 SMD0805 SMD1206 Radial 10 x 20 mm
SMD0603
Resistors 4 4 1 2 2 1 1 1 Inductor 1 L1 Inductor, 1.25 H, T60-18, 6 turns Easymagnet AP106019006P-1R1M na R1, R2, R20, R17 R3, R5, R11, R16 R4 R6, R9 R8, R13 R7 R19 R18 Resistor, 3R3, 1/16W, 1 % Resistor, 0R, 1/8W, 1 % SMD0805 Resistor, 1R8, 1/8W, 1 % Resistor, 2K2, 1/16W, 1 % Resistor, 3K9, 1/16W, 1 % Resistor, 18K, 1/16W, 1 % Resistor, 22K, 1/16W, 1 % Resistor, 20K, 1/16W, 1 % SMD0603 SMD0603
Active components 1 1 1 1 D1 Q5 Q7 U1 Diode, 1N4148 or BAT54 STD70N02L DPACK STD95NH02LT4 Controller, L6728 DFN10, 3x3 mm SOT23
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20 A demonstration board
L6728
12.1
12.1.1
Board description
Power input (Vin)
This is the input voltage for the power conversion. The High-Side drain is connected to this input. This voltage can range from 1.5 V to 12 V bus. If the voltage is between 4.5 V and 12 V it can supply also the device (through the Vcc pin) and in this case the R16 (0 ) resistor must be present.
12.1.2
Output (Vout)
The output voltage is fixed at 1.25 V but it can be changed by replacing the resistors R8 (sense partition lower resistor ) and R13 (feedback partition lower resistor). R18 allows to adjust OCP threshold.
12.1.3
Signal input (Vcc)
Using the input voltage Vin to supply the controller no power is required at this input. However the controller can be supplied separately from the power stage through the Vcc input (4.5-12 V) and, in this case, the R16 (0 ) resistor must be unsoldered.
12.1.4
Test points
Several test points are provided to have easy access at all important signal characterizing the device: - - - - - - - COMP: the output of the error amplifier; FB: the inverting input of the error amplifier; PGOOD: signaling the regular functioning (active high); VGDHS: the bootstrap diode anode; PHASE: Phase node; LGATE: Low-side gate pin of the device; HGATE: High-side gate pin of the device.
12.1.5
Board characterization
Figure 14. 20 A demonstration board efficiency
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L6728
5 A demonstration board
13
5 A demonstration board
L6728 demonstration board realizes in a two-layer PCB a step-down DC/DC converter and shows the operation of the device in a general-purpose low-current application. The input voltage can range from 5 V to 12 V buses and the output voltage is fixed at 1.25 V. The application can deliver an output current in excess of 5 A. The switching frequency is 300 kHz. Figure 15. L6728 - 5 A demonstration board (left) and components placement (right)
Figure 16. L6728 - 5 A demonstration board top (left) and bottom (right) layers
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GND
COMP
FB
OUT
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VIN1 GNDIN1
VIN_POWER
GNDIN_POWER
5 A demonstration board
0
R16 0 VCC D1 VCC GND BOOT C10 100nF HSD VIN_POWER GND C38 1uF R2 3.3 BAT54
VCC
GNDCC
0
5 /6
Q5a UGATE R3 PHASE 0 HSG1 4
0
C12 10uF
C51 10uF
3
0
0
VOUT1
R17 3.3 L2 PHASE PHASE PIN
VOUT
2
2.2uH
1
OUT C18 NC GNDOUT1 GNDOUT
VCC_PIN LGATE Q5b PGOOD R19 22k LGATE LSG1
7 /8
R4 1.8
2 1
C23 6.8nF
R5
0
U1 BOOT
1 BOOT 2 PHASE UGATE LGATE GND
R1 C14 1uF
PHASE PIN
L6728
VSEN FB COMP VCC 6
VCC_PIN VCC 3.3
PGOOD 9 8 7
COMP FB VSEN
10
0 0
0
0
UGATE
3 4 5
Figure 17. 5 A demonstration board schematic
LGATE R18 10k
OUT C29 NC
OUT C30 330uF
0
0
COMP
FB
OUT R7 4.7k C36 C35 R13 3.9k VSEN 220pF R14 15 6.8nF Vsen R6 68nF 22uF NC C24 R9 2.2k C39 C40
0
0
0
2.2k R8 3.9k
L6728
0
L6728 Table 7.
Qty Capacitors 2 1 2 1 1 2 1 1 Resistors 3 3 1 1 2 2 1 1 1 Inductor 1 L1 Inductor, 2.2 H, WURTH 744324220LF R1, R2, R17 R3, R5, R16 R4 R14 R6, R9 R8, R13 R7 R19 R18 Resistor, 3R3, 1/16 W, 1 % Resistor, 0R, 1/16 W, 1 % Resistor, 1R8, 1/8 W, 1 % Resistor, 15R, 1/16 W, 1 % Resistor, 2K2, 1/16 W, 1 % Resistor, 3K9, 1/16 W, 1 % Resistor, 4K7, 1/16 W, 1 % Resistor, 22K, 1/16 W, 1 % Resistor, 10K, 1/16 W, 1 % C12, C51 C10 C14, C38 C39 C30 C23, C36 C24 C35
5 A demonstration board 5 A demonstration board - bill of material
Reference Description Package
MLCC, 10 F, 25 V, X5R Murata GRM31CR61E106KA12 MLCC, 100 nF, 16 V, X7R MLCC, 1 F, 16 V, X7R MLCC, 22 F, 6.3 V, X5R Murata GRM31CR60J226ME19L 330 F, 6.3 V, 9 m Sanyo 6TPF330M9L MLCC, 6.8 nF, X7R MLCC, 68 nF, X7R MLCC, 220 pF, X7R
SMD1206 SMD0603 SMD0805 SMD1206 SMD7343
SMD0603
SMD0603
SMD0603
SMD0805
SMD0603
SMD0603
na
Active Components 1 1 1 D1 Q5 U1 Diode, BAT54 STS9D8NH3LL Controller, L6728 SOT23 SO8 DFN10, 3x3 mm
13.1
13.1.1
Board description
Power input (Vin)
This is the input voltage for the power conversion. The high-side drain is connected to this input. This voltage can range from 1.5 V to 12 V bus.
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5 A demonstration board
L6728
If the voltage is between 4.5 V and 12 V it can supply also the device (through the Vcc pin) and in this case the R16 (0) resistor must be present.
13.1.2
Output (Vout)
The output voltage is fixed at 1.25 V but it can be changed by replacing the resistors R8 (sense partition lower resistor ) and R13 (feedback partition lower resistor). R18 allows to adjust OCP threshold.
13.1.3
Signal input (Vcc)
Using the input voltage Vin to supply the controller no power is required at this input. However the controller can be supplied separately from the power stage through the Vcc input (4.5-12 V) and, in this case, the R16 (0 ) resistor must be unsoldered.
13.1.4
Test points
Several test points are provided to have easy access at all important signal characterizing the device: - - - - - - - COMP: the output of the error amplifier; FB: the inverting input of the error amplifier; PGOOD: signaling the regular functioning (active high); VGDHS: the bootstrap diode anode; PHASE: Phase node; LGATE: Low-side gate pin of the device; HGATE: High-side gate pin of the device.
13.1.5
Board characterization
Figure 18. 5 A demonstration board efficiency
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L6728
Package mechanical data
14
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com Table 8.
Dim. Min A A1 A2 A3 b D D2 E E2 e L M m 0.3 1.49 2.21 0.18 0.80 Typ 0.90 0.02 0.70 0.20 0.23 3.00 2.26 3.00 1.64 0.50 0.4 0.75 0.25 0.5 11.8 1.74 58.7 2.31 87.0 0.30 7.1 Max 1.00 0.05 Min 31.5 Typ 35.4 0.8 27.6 7.9 9.1 118.1 89.0 118.1 64.6 19.7 15.7 29.5 9.8 19.7 68.5 90.9 11.8 Max 39.4 2.0
DFN10 mechanical data
mm mils
Figure 19. Package dimensions
m
M
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Revision history
L6728
15
Revision history
Table 9.
Date 29-Jun-2007 17-Sep-2007 05-Jun-2008
Document revision history
Revision 1 2 3 Initial release Updated TJ value in Table 3: Thermal data on page 6 Added Figure 11 on page 21 Updated Section 14 on page 29, coverpage, Table 6 on page 23, Figure 17 on page 26, Table 7 on page 27 Changes
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L6728
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